Digital logic consists of combinational logic functions and sequential logic functions. In combinational logic functions, the digital output(s) is determined by the present data state of its input data signals. Any change in an input data state of combinational logic function results in an immediate change in the function's output data state. Examples of these combinational logic functions are AND gates (a TRUE state on ALL inputs results in a TRUE state on the output), OR gates (a TRUE state on ANY input results in a TRUE state on the output), and Multiplexers (the output state is derived from one of a set of inputs that is selected from another set of inputs). Sequential logic functions differ in that the output data state (Q) can maintain a data state that is dependent on the input data states that were applied in the past. The most commonly used sequential function in logic designs is the flipflop. The flipflop's output data (Q) state changes only when there is a positive transition on its input clock (C) signal. At the time of this transition, the output data (Q) state changes to the state on its input data (D) signal. After the clock signal transition, the output (Q) maintains its state regardless of the data input data state. Each clock transition is referred to as a data cycle. Normally these data cycles occur at regularly scheduled intervals which represent the effective data rate of the circuit. Normal operation of the circuit will typically involve millions of data cycles.
To add testability to a circuit, flipflops are modified to facilitate the setting and reading of their data states using a data path that is independent of the functional combinational logic. This is referred to as Design For Test (DFT). FIG. 1 depicts a circuit element consisting of four (4) flipflops with the combinational logic enclosed in a “black box” for simplicity. FIG. 2 depicts the same circuit with a scan chain implemented. This implementation involves adding a signal multiplexer in the data input (D) of each flipflop. A single control signal called Scan Enable is added to control the selection of these multiplexers. When the Scan Enable signal is low, the circuit works as normal, meaning the data input to the flipflops comes from the combinational logic. When scan enable is set to a “1” state, the input of each flipflop is connected to the output of another flipflop. The data input to the first flipflop in this scan chain is brought out to an external pin of the device. Likewise the data output of the last flipflop in the chain are brought out to an external pin (Scan Out of the device. FIG. 3 depicts how this implementation facilitates the shifting in of a test pattern on the Scan In pin to every flipflop in the circuit. After the test pattern is shifted in, the Scan Enable signal is brought low for one cycle and the data outputs of the combinational logic resulting from the shifted in test pattern is captured in the flip-flops. The Scan Enable signal is then brought back high and the captured data results are shifted out of the Scan Out pin and compared against expected results by the tester. Any operational defect in the combinational logic will cause one or more bits of the data output sequence to differ from the expected results.
Building upon the illustration of the principle discussed above, a typical IC design might implement thousands of flipflops in each scan chain, and employ multiple scan chains across the IC. Also there are commonly several thousand different scan patterns applied in a test (a single pattern refers to the complete set of sequential data that is shifted into each flipflop, requiring that each pattern contain one unique data state for each flip-flop in the design). This results in an extremely large volume of test data that is applied to and tested for during the testing of a complex IC. Moreover the multiple scan chains within a device will rarely if ever have exactly identical length so a test pattern will frequently have don't cares.
The role of IC test may to verify that an IC is free of any manufacturing defects. During the execution of a test pattern, if a data state is detected that is different then the expected data state, it may be economical to terminate the test and categorize the IC as defective. However it may be desirable to capture all failing data states in all patterns for the purpose of subsequently diagnosing the failures to determine which combinational logic element caused the fault. This diagnosis is normally done by a separate software program that analyzes the results captured by the automatic test equipment. The automatic test equipment must also be able to record the required information required to perform this post analysis process. FIG. 4 illustrates a chip with multiple scan chains. FIG. 5 depicts a conventional tester that facilitates this. A Data Pattern Memory is loaded with the test patterns to be applied to the IC, plus the data pattern expected to be read out of the IC. A tester may have a selectable modes either to terminate the test whenever an error occurs (an output data state differs from the expected data state), or to complete the entire pattern set and record all of the errors that were observed. To accomplish this, a tester would have a Data Capture Memory. This memory records the data cycle count and the output pin an error is observed on. Another mode of the Data Capture Memory is to record the actual states read from the IC outputs.
A single fault in the combinational logic may create several thousand errors to be potentially recorded in a data capture memory. As an example consider an IC design that has 20,000 flipflops in each scan chain, and applies 10,000 patterns. A single combinational logic fault might cause 10 flipflops to fail in 25% of the patterns. This would result in 25,000 failures being recorded in the Data Capture Memory. While non-trivial, this data can be managed to a reasonable degree and “datalogged” to a file for post processing to determine the location of the combinational logic fault.
However, a fault that exists in a scan chain path itself creates a significantly different diagnosis problem. FIG. 6 depicts the same example IC described before but with a “Short” at the input of the multiplexor going into flipflop #602. This defect will cause all scan in data to be “stuck-at” a “0” state in flipflops #601 and #602. This defect has two repercussions, 1) the test pattern applied to the combinational logic is invalid, and 2) upon scanning out, the blockage causes the inability to observe any data captured in flip-flop #603. The result is a tremendous number of fails.
This defect can be isolated by the following method. Consider an example device that has 30 flipflops and a defect exists that causes a “stuck-at” state of “0” at the input to flipflop #16. When applying the set of test patterns to the device, the “capture” events will capture non-deterministic data states from the combinations in all flipflops (the data is non-deterministic because of the invalid test pattern data after flipflop #15). The non-deterministic “0” and “1” data states captured in flipflops #1-15 will be observed when shifting out the data, but all captured data after flipflop #15 will be read as “0” data states. By observing at what cycle location in the output data stream that data stops transitioning between “1”'s and “0”'s and becomes a constant data state one could estimate at which flipflop the fault exists. FIG. 7 depicts an example of the data out pattern that might be observed in this example. Note that multiple patterns must be applied to determine the fault location since the non-deterministic data state in the observable flipflops might contain “0” data states. The estimate is not accurate until pattern #7 in the example. By executing a large number of patterns a higher degree of confidence is obtained. The disadvantage in this method is the large amount of data that must be recorded in the tester's data capture memory and analyzed. In the example where there are 20,000 flipflops in a chain, and 1000 patterns applied, 2,000,000 data states are captured and analyzed.
Thus it can be appreciated that what is needed is a way of determining a location of a fault in a scan chain without capturing, recording and analyzing millions of test failure data values.